Hybrid Floating Point Technique Yields 1.2 Gigasample Per Second 32 to 2048 point Floating Point FFT in a single FPGA (37K) Ray Andraka HPEC 2006, Proceedings of the Tenth Annual High Performance Embedded Computing Workshop, Poster Session B.4. Sept 19-21, 2006, Lincoln, MA. Discusses architecture of our ultra high speed Virtex4 floating point FFT.
An Onboard Processor and Adaptive Scanning Controller for the Second-Generation Precipitation Radar (1833K) Mark A. Fischman, Andrew C. Berkun, William W. Chun, Eastwood Im, and Ray Andraka. IEEE Transactions On Geoscience and Remote Sensing, Vol. 43 No. 4, April 2005 © IEEE, 2005 Included here by permission.
"Design and Verification of the Second-Generation Precipitation Radar Processor/Controller" Mark A. Fischman, Andrew C. Berkun, William W. Chun, Eastwood Im, Ray Andraka. 3rf Annual Earth Science Technology Conference (ETSC), June 24-26, 2003, University of Maryland Inn and Conference Center. Session B3P1. --
Design and Demonstration of an Advanced On-Board Processor for the Second-Generation Precipitation Radar (4126K) Mark A. Fischman, Andrew C. Berkun, Frank T. Cheng, William W. Chun, Eastwood Im, and Ray Andraka. Submitted to 2003 IEEE Aerospace Conference, Mar 8-15, 2003 . © IEEE, 2003 Included here by permission. This paper discusses the application of the radar processor described in the paper "FPGAs make a radar signal processor on a chip a reality". Lots of colorful graphics, hence the large size.
A Low Complexity Method for Detecting Configuration Upset in SRAM Based FPGAs (282K) Ray Andraka and Jennifer Brady, MAPLD 2002, Proceedings of the 2002 Military and Aerospace Applications of Programmable Devices and Technologies Conference, Sept 10-12, 2002, Laurel, MD. Introduces a technique based on built in self test for detecting configuration upset in FPGAs used in harsh environments.
FPGAs Make a Radar Signal Processor on a Chip a Reality (66K) Ray Andraka and Andrew Berkun, Proceedings of the 33rd Asilomar Conference on Signals, Systems and Computers, October 24-27, 1999, Monterey, CA. © IEEE, 1999 Included here by permission.This paper describes how we perform over 10 billion multiplications per second in one FPGA. The secret is distributed arithmetic, and this paper tells you how it is done. It also addresses digital demodulation and matched filtering in FPGAs.
An FPGA Based Processor Yields a Real Time High Fidelity Radar Environment Simulator (207K) Ray Andraka and Rick Phelps, MAPLD'98, Proceedings of the 1998 Military and Aerospace Applications of Programmable Devices and Technologies Conference, Sept 15-16, 1998, Greenbelt, MD. Discusses the significant benefits attained using a reconfigurable platform based on FPGAs rather than custom hardware to realize a high performance radar environment simulation. Benefits include board reuse, accelerated development schedule, enhanced testability and significantly easier debug.
A Survey of CORDIC Algorithms for FPGAs (121K) Ray Andraka, FPGA '98. Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, Feb. 22-24, 1998, Monterey, CA. pp191-200 (session 9, Novel FPGA Applications). © Copyright 1998 by ACM, Inc. Included here by permission, © ACM, Inc. Describes the CORDIC algorithm in layman's terms, and discusses implementation issues specific to FPGAs. The CORDIC algorithm is a shift-add algorithm for computing trigonometric, hyperbolic trigonometric and linear functions and their inverses. It can also be used for log, exponent and square root. Common uses are sine and cosine generation, vector magnitude, polar-cartesian conversions, and vector rotation. This is a "working copy" of the paper,which is identical to the camera-ready proof sent to ACM. The definitive version (1012K) is archived on the Association of Computing Machinery's website. To download the article from ACM, You need to first register on ACM's website. ACM charges a download fee for non-members. This 1998 CORDIC survey paper was selected as one of the 25 most influential FPGA papers in 2012 for the reasons outlined in the accompanying citation. It has been cited in over 1000 articles to date according to scholar.google.com
A Dynamic Hardware Video Processing Platform (50K) Ray Andraka, Conference on Reconfigurable Technology for Rapid Product Development and Computing, SPIE Photonics East ‘96, November 1996 Examines use of an FPGA as the processing element in a video processing system. Use of customized overlays on a foundation containing interfaces and common circuits speeds development time.
Building a High Performance Bit Serial Processor in an FPGA (379K) Ray Andraka, On-Chip Design Conference, Design SuperCon '96, Jan 1996. A discussion of high speed bit serial design techniques for FPGAs. The paper examines a CORDIC vector magnitude computer designed for a radar signal processor.
FIR filter fits in an FPGA: A bit serial Approach (66K) Ray Andraka, 3rd PLD Conference, March 1993 Presentation of design techniques to realize a 27 tap 12 bit FIR filter in a single FPGA.