How to build Ultra-Fast Floating-Point FFTs in FPGAs (254K) Ray Andraka, DSP Design Line, April 30, 2007, Featured How-to. Reprint of the Xilinx DSP Magazine article.
Supercharge Your DSP with Ultra-Fast Floating-Point FFTs (254K) Ray Andraka, Xilinx DSP Magazine, Issue 3, April 2007, pp42-44. Discusses the algorithm and architecture of our ultra high speed Virtex4 floating point FFT.
Ultrafast Processor for Interferometric Radar by Mark A. Fischman, Marc Simard, and Ray Andraka. NASA Tech Briefs, March 2006 Issue, page #14ET NPO-42026
FPGAs "DiSP"lay their processing prowess Brian Dipert, Technical Editor. EDN Magazine design feature, Issue 22, Oct 3, 2002, pp 61-68. Article highlights using FPGAs as digital signal processors. This article features a sidebar by Ray Andraka.
High Performance Digital Down-Converters for FPGAs Ray Andraka, president, Andraka Consulting Group, Inc., Xilinx Xcell Journal issue #38, fourth quarter 2000, pp48-51. Andraka Consulting has been a leader in digital radio applications using FPGAs. This article discusses implementation of digital downconverters in FPGAs.
FPGAs cut power with 'pipeline' Ray Andraka, president, Andraka Consuting Group, Inc., EE Times, August 7, 2000 pp 84-88. And online in EETimes.com Using FPGAs instead of DSP processors improves performance and lowers power. This article tells you why.
FPGA synthesis tools lose battle with John Henry Craig Matsumoto, EE Times.com, February 14, 2000. Monterey, CA. Coverage of the FPGA2000 Panel discussion evaluating the ability of CAE tools for FPGAs. The resounding conclusion: There will always be a place for the expert.
Counting on Gate Counts? Don't count on it Brian Dipert, Technical Editor. EDN Magazine cover story, Issue 16, August 3, 1998. Discussion of gate counting methodologies for FPGAs. Andraka Consulting Group is a technical contributor to the article.
Beat the heat on power consumption Brian Dipert, Technical Editor. EDN Magazine design feature, Issue 16, August 1, 1997. Discussion of design techniques to help control power consumption in FPGAs. Andraka Consulting Group is a technical contributor to this article.
Shattering the Programmable Logic Speed Barrier Brian Dipert, Technical Editor. EDN Magazine cover story, Issue 11, May 22, 1997. Discussion of techniques needed to obtain a high performance FPGA design. This article contains a sidebar featuring tips by Andraka Consulting Group.